MOS solid-state imaging devices can be broadly divided into two types, an AMI type and a floating diffusion amplifier type (may be referred to as an “FDA type” hereinafter), according to the circuit configuration and the timing when charges accumulated in a pixel unit of a photoelectric transducer PD are detected.
FIG.1 is a diagram showing a configuration of the AMI type solid-state imaging device.
As shown in FIG. 1, a solid-state imaging device 900 includes; plural pixel units 10an1 and 10an2 which are arranged two-dimensionally (two units in the diagram); plural common column signal lines Lns respectively arranged per column (a line in the diagram); a load transistor Q2la connected to each common column signal line Ln; a sample hold transistor Q31 provided for each common column signal line Ln; plural noise signal elimination circuits 40 which are respectively arranged per column (a circuit in the diagram); and the like.
Each of the pixel units 10an1 and 10an2 includes: a photoelectric transducer PD which converts incident light to charges; a reset transistor Q12 which resets a cathode of the photoelectric transducer PD to a power supply voltage VDD using a RESET pulse; a voltage conversion amplifying transistor Q13a which detects a voltage corresponding to charges of the photoelectric transducer PD; and a row selection transistor Q14 which transfers, to each of the common column signal lines Lns per row, a voltage outputted from the voltage conversion amplifying transistor Q13 using a VSEL pulse.
The sample hold transistor Q31 samples and holds the voltage outputted to the common column signal line Ln using an SH pulse.
The noise signal elimination circuit 40 includes a clamp transistor Q42, a clamp capacitor C41, and a sample hold capacitor C42, and detects a signal component in which a noise component is eliminated, by obtaining a difference between: a reset voltage of the photoelectric transducer PD to be detected in each of the pixel unit 10an1 and 10an2; and a voltage to be detected depending on the charges corresponding to the amount of light.
Next, a charge detection operation of the solid-state imaging device 900 is described. Note that the charge detection operation in the pixel unit 10an1 is described in particular.
FIG. 2 is a diagram showing drive timing of the solid-state imaging device 900 shown in FIG. 1.
At the time t0, all pulses are off.
Next, the VSE pulse turns on the row selection transistor Q14 at the time t0, the SH pulse turns on the sample hold transistor Q31 at the time t2, and a CP pulse turns on the clamp transistor Q42 in the noise signal elimination circuit 40 from the time t3 to t4.
From the time t4 when the CP pulse is turned off to the time t5 when the RESET pulse in the pixel unit 10an1 is turned on, the sample hold capacitor C42 in the noise signal elimination circuit 40 holds the accumulated charges of the photoelectric transducer PD of the pixel unit 10an1 via the voltage conversion amplifying transistor Q13a of the pixel unit 10an1.
A holding signal in this case is assumed to be a voltage A.
From the time t5 to the time t6, after the RESET pulse turns on the reset transistor Q12 and then the photoelectric transducer PD is reset to a power supply voltage VDD level, until the time when the SH pulse turns off the sample hold transistor Q31 at the time t7, the sample hold capacitor C42 of the noise signal elimination circuit 40 again hold the reset level of the photoelectric transducer PD via the voltage conversion amplifying transistor Q13a. The holding signal at this time is assumed to be a voltage B. In the noise signal elimination circuit 40, by obtaining a difference between the previously held voltage A and the subsequently held voltage B, an accumulation signal component is detected which is in a two-dimensional imaging region of the pixel units and in which the noise signal component is eliminated. Next, at the time t8, the VSEL pulse turns off the row selection transistor Q14. With this, the charge detection operation for a row of the photoelectric transducer PD set in the two-dimensional imaging region ends.
FIG.3 is a diagram showing the configuration of an FDA-type solid-state imaging device.
In this case, a solid-state imaging device 950 includes pixel units 10bn1 and 10bn2 as a replacement for the pixel units 10an1 and 10an2.
Each of the pixel units 10bn1 and 10bn2 further includes a transfer transistor Q11 which reads charges from the photoelectric transducer PD and a floating diffusion FD which temporarily accumulates charges, in addition to the components provided for the pixel units 10an1 and 10an2. In this case, the reset transistor Q12a resets the floating diffusion FD to the power supply voltage VDD, and the voltage conversion amplifying transistor Q13a detects a voltage corresponding to the accumulated charges of the floating diffusion FD.
Next, the charge detection operation of the solid-state imaging device 950 is described. Note that the charge detection operation in the pixel unit 10bn1 is described in particular.
FIG. 4 is a diagram showing drive timing of the solid-state imaging device 950.
At the time t0, all pulses are OFF. Next, the VSEL pulse turns on the row selection transistor Q14 of the pixel unit 10bn1 at the time t1, and the SH pulse turns on the sample hold transistor Q31 at the time t2. From the time t3 to t4, the RESET pulse turns on the reset transistor Q12a. With this, after the floating diffusion FD is reset to the power supply voltage VDD level, from the time t4 when the RESET pulse is turned off to the time t5 when the TRANS pulse turns on the transfer transistor Q11, the sample hold capacitor C42 of the noise signal elimination circuit 40 holds the reset level of the floating diffusion FD via the voltage conversion amplifying transistor Q13a. The holding signal at this time is assumed to be a voltage C.
Next, from the time t5 to the time t6, the TRANS pulse turns on the transfer transistor Q11, and after the accumulated charges of the photoelectric transducer PD are transferred to the floating diffusion FD, until the time t7 when the SH pulse turns off the sample hold transistor Q31, the sample hold capacitor C42 of the noise signal elimination circuit 40 holds the charges accumulated in the floating diffusion FD of the pixel unit 10bn1 via the voltage conversion amplifying transistor Q13a. The holding signal at this time is assumed to be a voltage D. In the noise signal elimination circuit 40, by obtaining a difference between the previously held voltage C and the subsequently held voltage D, an accumulation signal component is detected which is in the two-dimensional imaging region of the pixel units and in which the noise signal component is eliminated. Next, at the time t8, the VSEL pulse turns off the row selection transistor Q14. With this, the charge detection operation for a row of the photoelectric transducer PD set in the two-dimensional imaging region ends.
However, when a subject is captured with a high-luminance light, such as sunlight, for a background, a phenomenon occurs that the aforementioned MOS solid-state imaging device detects a portion of the high-luminance subject not as a saturation signal level but as a no-signal level.
The occurrence mechanism of this phenomenon is described with reference to FIGS. 5 to 9. The pixel unit 10an1 loans used in FIG. 5 and FIG. 6 is categorized as an AMI type. FIG. 5 shows a case where the amount of incident light is reference amount of light, and normal charge detection is performed. FIG. 6 shows a case where the amount of incident light is equal to or more than 200 thousand times as much as the reference amount of light, and abnormal charge detection is performed.
FIG. 5(a) shows a potential diagram of the pixel unit 10an1 from the time t3 to the time t5 shown in FIG. 2.
The noise signal elimination circuit 40 holds the accumulated charges of the photoelectric transducer PD via an voltage conversion amplifier of the pixel unit 10an1. The holding signal at this time is assumed to be the voltage A.
FIG. 5(b) shows a potential diagram of the pixel unit 10an1 from the time t5 to the time t6 shown in FIG. 2. Here, the photoelectric transducer PD is reset to the power supply voltage VDD level.
FIG. 5(c) shows a potential diagram of the pixel unit 10an1 from the time t6 to the time t7 shown in FIG. 2. Here, the level of the photoelectric transducer PD which has been reset to the power supply voltage VDD level is maintained, and is held by the noise signal elimination circuit 40 via the voltage conversion amplifier of the pixel unit 10an1. The holding signal at this time is assumed to be the voltage B. In the noise signal elimination circuit 40, by obtaining a difference between the previously held voltage A and the subsequently held voltage B, an accumulation signal component can be detected which is in the two-dimensional imaging region of the pixel units and in which the noise signal component is eliminated.
FIG. 6(a) shows a potential diagram of the pixel unit 10an1 from the time t3 to the time t5 shown in FIG. 2. Here, the noise signal elimination circuit 40 holds the accumulated charges of the photoelectric transducer PD via a voltage conversion amplifier of the pixel unit 10an1, The holding signal at this time is assumed to be the voltage A.
FIG. 6(b) shows a potential diagram of the pixel unit 10an1 from the time t5 to the time t6 shown in FIG. 2. Here, the photoelectric transducer PD is reset to the power supply voltage VDD level.
FIG. 6(c) shows a potential diagram of the pixel unit 10an1 from the time t6 to the time t7 shown in FIG. 2. Here, the level of the photoelectric transducer PD which has been reset to the power supply voltage VDD level can not be maintained. In the case where the amount of incident light is equal to or more than 200 thousand times as much as the reference amount of light, immediately after the photoelectric transducer PD is reset to the power supply voltage VDD level, in other words, immediately after the time t6 when the RESET pulse of the pixel unit 10an1 is turned off, the large amount of charges is accumulated in the photoelectric transducer PD. Thus, the voltage level identical to the level when the accumulated charges become saturated is held by the noise signal elimination circuit 40 via the voltage conversion amplifier of the pixel unit 10an1. In this case, assuming that the holding signal is the voltage B, a difference between the previously held voltage A and the subsequently held voltage B becomes 0 or minus in the noise signal elimination circuit 40. As a result, the accumulation signal component can not be detected which is in the two-dimensional imaging region of the pixel units and in which the noise signal component is eliminated.
The pixel unit 10bn1 described in FIG. 7 and FIG. 8 is categorized as an FDA type. FIG. 7 shows a case where the amount of incident light is the reference amount of light, and the normal charge detection is performed. FIG. 8 shows a case where the amount of incident light is equal to or more than 200 thousand times as much as the reference amount of light intensity, and the abnormal charge detection is performed.
FIG. 7(a) shows a potential diagram of the pixel unit 10bn1 from the time t3 to the time t5 shown in FIG. 4. Here, the RESET pulse of the pixel unit 10bn1 turns on the reset transistor Q12a. With this, a charge detection unit (floating diffusion) of the pixel unit 10bn1 is reset to the power supply voltage VDD level.
FIG. 7(b) shows a potential diagram of the pixel unit 10bn1 from the time t4 to the time t5 shown in FIG. 4. Here, the charge detection unit (floating diffusion) of the pixel unit 10bn1 which has been reset to the power supply voltage VDD level is maintained, and is held by the noise signal elimination circuit 40 via the voltage conversion amplifying transistor Q13a of the pixel unit 10bn1. The holding signal at this time is assumed to be the voltage C.
FIG. 7(c) shows a potential diagram of the pixel unit 10bn1 from the time t5 to the time t7 shown in FIG. 4.
After the accumulated charges of the photoelectric transducer PD are transferred to the charge detection unit (floating diffusion), the level is maintained. Until the time t7 when the SH pulse turns off the sample hold transistor Q31, the noise signal elimination circuit 40 holds the charges accumulated in the charge detection unit (floating diffusion) of the pixel unit 10bn1 via the voltage conversion amplifying transistor Q13a. The holding signal at this time is assumed to be the voltage D.
In the noise signal elimination circuit 40, by obtaining a difference between the previously held voltage C and the subsequently held voltage D, the accumulation signal component can be detected which is in the two-dimensional imaging region of the pixel units and in which the noise signal component is eliminated.
FIG. 8(a) shows a potential diagram of the pixel unit 10bn1 from the time t3 to the time t4 shown in FIG. 4. Here, the RESET pulse turns on the reset transistor Q12a. With this, the charge detection unit (floating diffusion) of the pixel unit 10bn1 is reset to the power supply voltage VDD level.
FIG. 8(b) shows a potential diagram of the pixel unit 10bn1 from the time t4 to the time t5 shown in FIG. 4. Here, the charge detection unit (floating diffusion) of the pixel unit 10bn1 which has been reset to the power supply voltage VDD level can not be maintained. In the case where the amount of incident light is equal to or more than 200 thousand times as much as the reference amount of light, with the parasitic NPN configuration as shown in FIG. 9, the potential in the photoelectric transducer PD region is significantly lowered, and a path where a current flows is generated from the charge detection unit (floating diffusion). With this, even when the TRANS pulse is turned off, the potential is lowered in the charge detection unit (floating diffusion) of the pixel unit 10bn1, and consequently, the noise signal elimination circuit 40 holds, via the voltage conversion amplifying transistor Q13a, the voltage level equal to or more than the level when the accumulated charges become saturated. The holding signal at this time is assumed to be the voltage C.
FIG. 8(c) shows a potential diagram of the pixel unit 10bn1 from the time t5 to the time t7 shown in FIG. 4. Here, even when the TRANS pulse of the pixel unit 10bn1 turns on the transfer transistor Q11, since the accumulated charges, equal to or more than the level when the accumulated charges become saturated, have flown from the photoelectric transducer PD in advance, the voltage level of the charge detection unit (floating diffusion) of the pixel unit 10bn1 is lowered. Consequently, the noise signal elimination circuit 40 holds this voltage level via the voltage conversion amplifying transistor Q13a of the pixel unit 10bn1. Assuming that this holding signal is the voltage D, a difference between the previously held voltage C and the subsequently held voltage D becomes 0 or minus. As a result, the accumulation signal component can not be detected which is in the two-dimensional imaging region of the pixel units and in which the noise signal component is eliminated (refer to Patent Reference 1).
As a method of solving this phenomenon, a method which detects a pixel output signal in a signal processing circuit and corrects it is suggested (refer to Patent Reference 2).
When a subject is captured with a high-luminance light, such as sunlight, for a background, a conventionally suggested correction method is to temporarily transfer an output signal generated immediately after a photoelectric transducer PD or a charge detection unit is reset to a comparator in a signal processing circuit and then to judge whether or not high-luminance light is entered using the voltage.    Patent Reference 1: Japanese Laid-Open Patent Application No. 2003-46865 (Pages 1-8, FIG. 1)    Patent Reference 2: Japanese Laid-Open Patent Application No. 2000-287131 (Pages 1-16, FIG. 1)